Although a static RAM (Random-Access Memory) has the disadvantage that many elements are needed to configure each memory cell, it has the advantage that it stores data continuously without requiring a refresh operation as long as a source voltage is applied so as to achieve a high-speed writing/reading. In general, in the case of a static RAM, a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters are used to configure each flip-flop circuit. More specifically, two CMOS inverters, each configured by connecting a PMOS (P-channel MOS) transistor and an NMOS (N-channel MOS) transistor in series, are connected in parallel between a source voltage terminal at source voltage VDD and a source voltage at ground potential VSS, and the input terminal and the output terminal of each inverter are connected to the output terminal and the input terminal of the other inverter by means of cross-coupling in order to configure a single bistable circuit or a flip-flop circuit with a pair of data storage nodes.
In general, in the case of a memory cell of this type, the pair of data storage nodes are connected to a pair of complementary bit lines via a pair of transfer gate transistors which are turned on and off via word lines. To write data to the memory, both bit lines are driven or precharged to two types of complementary (opposite logic levels) potentials according to the logic value of the data to be written in order to turn on both transfer gate transistors, and voltage signals on the bit lines are input (written) into the respective data storage nodes via the transfer gate transistors. To read stored data from the memory cell, both transfer gate transistors are turned on simultaneously in order to output the voltages of the data storage nodes to the respective bit lines via the transfer gate transistors, and the voltage signal(s) on one or both of the bit lines is/are detected in the form of binary values in order to generate the read data. To keep stored data in the memory, both transfer gate transistors should be kept off. However, source voltage VDD must be applied constantly. If the application of source voltage VDD is stopped, the supply of a data latch current to the data storage node on the side where an H-level voltage is clamped is stopped, and the data stored will be lost.
Furthermore, in the case of a multi-port static RAM, two or more sets of data can be written or read simultaneously in one cycle, and a write and a read can be carried out simultaneously in one cycle.
As described above, because the static RAM configured using the CMOS circuit consumes little current during operation or in stand-by, it is widely used in products and systems such as portable equipment which contains a small number of components. However, in recent CMOS fabrication technology, although the spread of MOS transistors have increased with further miniaturization, the leakage current has increased, exposing the dilemma between increasing speed and reducing power consumption. Nevertheless, in actual products, applications that require high-speed operation and reduced power consumption, for example, the processing of moving pictures on cellular telephones, continue to increase. That is, a power reduction technology capable of handling both the limitation of the CMOS process and requirements of actual products is in demand.
The present invention was conceived in the light of the aforementioned problem, and its purpose is to present a semiconductor device, a semiconductor memory, and a semiconductor memory cell with which the data latching current and the current consumed during standby can be significantly decreased in order to realize decreased power consumption.